`include "defines.v"
module CPU(
  input clk,
  input rst_n,
  // 用户定义的可屏蔽中断 不影响核心运行的中断
  input user_interrupt,
  // 不可屏蔽的关键中断 例如 UPS断电信号 核心外设错误信号
  input sys_interrupt,
  /* AXI Master */
  input     [31:0]                    boot_addr,
  /* AR  */
  input                               axi_ar_ready  ,
  output                              axi_ar_valid  ,
  output [`AXI_ADDR_WIDTH-1:0]        axi_ar_addr   ,
  output [2:0]                        axi_ar_prot   ,
  output [`AXI_ID_WIDTH-1:0]          axi_ar_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_ar_user   ,
  output [7:0]                        axi_ar_len    ,
  output [2:0]                        axi_ar_size   ,
  output [1:0]                        axi_ar_burst  ,
  output                              axi_ar_lock   ,
  output [3:0]                        axi_ar_cache  ,
  output [3:0]                        axi_ar_qos    ,
  /* R */
  output                              axi_r_ready   ,
  input                               axi_r_valid   ,
  input  [1:0]                        axi_r_resp    ,
  input  [`AXI_DATA_WIDTH-1:0]        axi_r_data    ,
  input                               axi_r_last    ,
  input  [`AXI_ID_WIDTH-1:0]          axi_r_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_r_user    ,
  /* AW */
  input                               axi_aw_ready  ,       
  output                              axi_aw_valid  ,   
  output [`AXI_ADDR_WIDTH-1:0]        axi_aw_addr   ,   
  output [2:0]                        axi_aw_prot   ,   
  output [`AXI_ID_WIDTH-1:0]          axi_aw_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_aw_user   ,     
  output [7:0]                        axi_aw_len    ,      
  output [2:0]                        axi_aw_size   ,
  output [1:0]                        axi_aw_burst  ,
  output                              axi_aw_lock   ,   
  output [3:0]                        axi_aw_cache  ,   
  output [3:0]                        axi_aw_qos    ,   
  /* W */
  input                               axi_w_ready   ,  
  output                              axi_w_valid   ,
  output [`AXI_DATA_WIDTH-1:0]        axi_w_data    ,   
  output [`AXI_DATA_WIDTH/8-1:0]      axi_w_strb    ,   
  output                              axi_w_last    ,   
  /* B */
  output                              axi_b_ready   ,
  input                               axi_b_valid   ,
  input  [1:0]                        axi_b_resp    ,  
  input  [`AXI_ID_WIDTH-1:0]          axi_b_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_b_user      
);

core rena_v2_core(
  .clk  (clk  ),
  .rst_n(rst_n),
  // 用户定义的可屏蔽中断 不影响核心运行的中断
  .user_interrupt(user_interrupt),
  // 不可屏蔽的关键中断 例如 UPS断电信号 核心外设错误信号
  .sys_interrupt(sys_interrupt),
  // boot mode
  .boot_addr(boot_addr),
  /* AXI Master */
  /* AR  */
  .axi_ar_ready (axi_ar_ready ) ,
  .axi_ar_valid (axi_ar_valid ) ,
  .axi_ar_addr  (axi_ar_addr  ) ,
  .axi_ar_prot  (axi_ar_prot  ) ,
  .axi_ar_id    (axi_ar_id    ) ,
  .axi_ar_user  (axi_ar_user  ) ,
  .axi_ar_len   (axi_ar_len   ) ,
  .axi_ar_size  (axi_ar_size  ) ,
  .axi_ar_burst (axi_ar_burst ) ,
  .axi_ar_lock  (axi_ar_lock  ) ,
  .axi_ar_cache (axi_ar_cache ) ,
  .axi_ar_qos   (axi_ar_qos   ) ,
  /* R */
  .axi_r_ready   (axi_r_ready ),
  .axi_r_valid   (axi_r_valid ),
  .axi_r_resp    (axi_r_resp  ),
  .axi_r_data    (axi_r_data  ),
  .axi_r_last    (axi_r_last  ),
  .axi_r_id      (axi_r_id    ),
  .axi_r_user    (axi_r_user  ),
  /* AW */
  .axi_aw_ready (axi_aw_ready ) ,       
  .axi_aw_valid (axi_aw_valid ) ,   
  .axi_aw_addr  (axi_aw_addr  ) ,   
  .axi_aw_prot  (axi_aw_prot  ) ,   
  .axi_aw_id    (axi_aw_id    ) ,
  .axi_aw_user  (axi_aw_user  ) ,     
  .axi_aw_len   (axi_aw_len   ) ,      
  .axi_aw_size  (axi_aw_size  ) ,
  .axi_aw_burst (axi_aw_burst ) ,
  .axi_aw_lock  (axi_aw_lock  ) ,   
  .axi_aw_cache (axi_aw_cache ) ,   
  .axi_aw_qos   (axi_aw_qos   ) ,   
  /* W */
  .axi_w_ready  (axi_w_ready   ) ,  
  .axi_w_valid  (axi_w_valid   ) ,
  .axi_w_data   (axi_w_data    ) ,   
  .axi_w_strb   (axi_w_strb    ) ,   
  .axi_w_last   (axi_w_last    ) ,   
  /* B */
  .axi_b_ready  (axi_b_ready ) ,
  .axi_b_valid  (axi_b_valid ) ,
  .axi_b_resp   (axi_b_resp  ) ,  
  .axi_b_id     (axi_b_id    ) ,
  .axi_b_user   (axi_b_user  )   
);

endmodule